This invention relates generally to a method and apparatus for simulating the operation of digital circuit designs to detect timing errors in the design.
In the design of a digital circuit, the circuit designer typically selects from a variety of commercially available components or elements (herein "circuit elements") and connects them in a configuration for achieving the desired circuit. To assure that each basic circuit element functions correctly, the circuit design must accommodate all of the timing constraints of each element. For example, a memory element typically requires a minimum setup time on all address inputs before the activation of a strobe or clock signal. The circuit elements which provide the address and strobe signals must accordingly comply with these timing constraints if the correct function is to be implemented.
Similarly, following the initiation of a read cycle, the memory device supplies data to its output lines within some memory delay interval. The minimum speed with which the memory device responds to a read request will often determine whether the circuit signals meet the timing constraints of other circuit elements connected downstream from the memory device. Determining whether the timing constraints of all elements are satisfied becomes increasingly complicated as the number of layers of logic and the circuit complexity increase.
Designers can often isolate and correct timing violations by constructing and debugging a prototype circuit. However, debugging a prototype is particularly difficult with custom designed integrated circuits (ICs) since modifications to the IC cannot readily be implemented as with discrete circuit designs. Further, eliminating timing problems from a given prototype does not assure that other embodiments of the design will be free of timing problems. For example, due to manufacturing variations, a first memory chip can require a first setup time for all address bits during a read cycle while a second memory chip of the same design requires a slightly greater set up time. Thus, a prototype circuit made with the first memory chip can operate without error while a prototype made with the second could fail.
To assist circuit designers, manufacturers of circuit elements typically provide specifications which indicate the range over which an element's timing constraints will vary. However, assuring that every element of a circuit design meets all possible combinations of timing constraints for every element is complicated. Computer simulation of circuit designs is now widely used to assist designers in locating timing violations, particularly in complicated designs.
A dynamic timing analysis performs timing verification by simulating the operation of the circuit in response to a specified pattern of inputs. First, for each element, timing characteristics (e.g., gate delays and fixed setup times) are assigned which are within the range of possible timing characteristics for the element as specified by the manufacturer. The selected timing constraints, in effect, define a prototype of the circuit whose components have the selected characteristics. The computer then simulates the operation of the prototype circuit in response to a sequence of patterns.
A simulation approach which has found application in the area of system and circuit reliability assessment is the Monte Carlo technique. Monte Carlo reliability analysis involves the statistically random substitution of critical components having a spectrum of performance parameters ranging from a known minimum and maximum value. An example of a classical Monte Carlo analysis for a simple analog circuit might consist of the evaluation of the circuit performance using various values of a 100 ohm, 10% resistors. Resistor values ranging from a minimum of 90 ohms to a maximum of 110 ohms would be randomly substituted, and for each substitution the circuit would be resimulated to test for satisfactory performance. As the number of satisfactory random simulations increases, the assurance that the circuit will perform adequately over the 20 ohm resistance range correspondingly increases.
The principal drawback of the traditional Monte Carlo technique as applied to dynamic timing analysis is that the number of simulations required to have any reasonable confidence in the yield rate due to the numerous possible timing constraints is unmanageably high. A typical circuit may have hundreds of thousands of circuit elements each potentially having multiple timing constraints. For each time constraint a statistically significant number of simulations must be performed. And finally, for each simulation, a variety of varying input patterns must be tested. The number of simulations using this classical approach could easily reach the thousands.
What is needed is a more efficient method and apparatus for simulating digital circuit designs,